1. Field of the Invention
The invention relates generally to integrated circuits and, more particularly, to multiple-output Static CMOS logic gate circuits that are capable of simultaneously computing more than one logic function.
2. Description of the Related Art
In integrated circuits, one common objective is to generate digital output(s) from digital input(s) where the digital output(s) are predetermined functions of the digital input(s). Traditionally, integrated circuits satisfy this objective via a logic circuit that uses electronic devices called gates, which utilize Boolean algebra to perform “combinational” tasks. For example, a logic circuit can be designed that multiplies two numbers A and B (inputs) to produce and output C. In this case, Boolean AND logic would be implemented to multiply the two numbers A and B to produce the output C.
Complementary Metal-Oxide Semiconductor (CMOS) transistors are commonly used to build gates on integrated circuits. CMOS transistors can be viewed as three-terminal electrically controlled switches. The gate terminal is the control input. The source and the drain terminals are either connected or disconnected depending on the voltage at the gate terminal. A transistor is ON when the source and the drain are connected and OFF otherwise. The transistors are one of two types: nMOS (negative polarity) transistors and pMOS (positive polarity) transistors. Specifically, nMOS transistors turn ON when a logic ‘1’ is applied to the gate terminal and pMOS transistors turn ON when a logic ‘0’ is applied to the gate terminal.
CMOS logic gates can be structurally implemented using approaches that include domino logic and static CMOS logic. These CMOS logic gates are built from networks of transistors connected in parallel or series. They receive one or more inputs and produce a single output. In a conventional static CMOS logic gate, a pull-down network of nMOS transistors is connected between the output and the ground, and a pull-up network of pMOS transistors is connected between the output and the power. The inputs control the gates of the transistors so that either the NMOS network or the pMOS network is ON at any given time, which drives the output to either a logic ‘0’ value or a logic ‘1’ value. In contrast, the pMOS pull-up network in a domino logic gate is removed and replaced with a precharge transistor.
In the case where multiple logic functions (i.e. multiple outputs) are required for digital circuit to perform a particular task, multiple logic gates (each producing only one output) must be linked together to produce multiple outputs. The result of using multiple logic gates is that the area and the power consumption of the circuit are increased in proportion to the number of transistors used—i.e. the greater the number of logic gates, the greater the number of transistors. To overcome this need for multiple logic gates, multiple-output domino logic gate designs have been developed which share transistors in the pull-down network to simultaneously compute several related logic functions (i.e. a single domino logic gate produces multiple outputs). However, domino circuits have become increasingly difficult to use because of problems of leakage, coupling, process variation, supply noise, clock skew, and productivity etc.
In view of the foregoing, there is a need for a systematic design of multiple-output Static CMOS logic gates that share transistors when computing multiple functions from a common set of inputs.